KK74HC112A Datasheet | Kodenshi AUK Group

TECHNICAL DATA Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The KK74HC112A is identical in pinout to the LS/ALS112. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LS/ALSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA - High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HC112AN Plastic KK74HC112AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H H PIN 16=VCC PIN 8 = GND H H Reset H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q H L L - Q L H L- H L No Change L H Toggle No Change No Change No Change - Both output will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously X = Don’t Care ..net MAXIMUM RATINGS- Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL - Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ±50 750 500 -65 to +150 260 Unit V V V m A m A m A m W °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Remended Operating Conditions. +Derating - Plastic DIP: - 10 m W/°C from 65° to 125°C SOIC Package: : - 7 m W/°C from 65° to 125°C REMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage...