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KP85302 - Half Bridge Gate Driver

Download the KP85302 datasheet PDF. This datasheet also covers the KP85301 variant, as both devices belong to the same half bridge gate driver family and are provided as variant models within a single manufacturer datasheet.

General Description

The KP8530X is a 650V half bridge gate driver with integrated bootstrap diode.

The typical source and sink current is 300mA and 600mA respectively.

KP8530X targeted to drive power MOSFETS.

Key Features

  • Fully Operational up to 650V.
  • Peak Output Current 0.3A Source, 0.6A Sink.
  • Integrated Fast Bootstrap Diode.
  • dV/dt Immunity of 50V/ns.
  • Logic Operational up to -7V on VS Pin.
  • Negative Voltage Tolerance on Inputs of - 5V.
  • Independent UVLO for Both Channels.
  • Small Propagation Delay (175ns Typical).
  • Delay Matching (15ns Typical).
  • Dual Inputs with Output Interlock.
  • 3.3V, 5V and 15V Input Logic Compatible.
  • Schmitt Trigger Input with Hysteresis.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (KP85301-Kiwi.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number KP85302
Manufacturer Kiwi
File Size 384.27 KB
Description Half Bridge Gate Driver
Datasheet download datasheet KP85302 Datasheet

Full PDF Text Transcription for KP85302 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for KP85302. For precise diagrams, and layout, please refer to the original PDF.

KP8530X 650V/300mA,600mA Half Bridge Gate Driver with Integrated Bootstrap Diode FEATURES  Fully Operational up to 650V  Peak Output Current 0.3A Source, 0.6A Sink  In...

View more extracted text
erational up to 650V  Peak Output Current 0.3A Source, 0.6A Sink  Integrated Fast Bootstrap Diode  dV/dt Immunity of 50V/ns  Logic Operational up to -7V on VS Pin  Negative Voltage Tolerance on Inputs of - 5V  Independent UVLO for Both Channels  Small Propagation Delay (175ns Typical)  Delay Matching (15ns Typical)  Dual Inputs with Output Interlock  3.