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ML610Q329 - 8-bit Microcontroller

Download the ML610Q329 datasheet PDF. This datasheet also covers the ML610Q327 variant, as both devices belong to the same 8-bit microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

Equipped with a 8-bit CPU nX-U8/100, the ML610Q327/338/339 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as timer, PWM, UART, I2C bus interface, synchronous serial port, successive approximation type 10-bit A/D converter and voice output function

Key Features

  • CPU.
  • 8-bit RISC CPU (CPU name: nX-U8/100).
  • Instruction system: 16-bit instructions.
  • Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on.
  • On-Chip debug function.
  • Minimum instruction execution time Approx 30.5 s (@32.768kHz system clock) Approx 0.244 s (@4.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ML610Q327-LAPIS.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ML610Q329
Manufacturer LAPIS
File Size 1.00 MB
Description 8-bit Microcontroller
Datasheet download datasheet ML610Q329 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ML610Q327/38/39 8-bit Microcontroller with Voice Output Function FEDL610Q339-01 Issue Date: Apr. 18, 2022 GENERAL DESCRIPTION Equipped with a 8-bit CPU nX-U8/100, the ML610Q327/338/339 is a high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as timer, PWM, UART, I2C bus interface, synchronous serial port, successive approximation type 10-bit A/D converter and voice output function. The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture.