Description
4.1 SCbus Interface 4.2 External Buffering for SCbus Signals 4.3 CW4010 Shell Interface 4.4 Mbus Interface 4.5 Lbus Interface 4.6 Phase-Locked Loop (PLL) Clock Signals 4.6 Test Signals 4.7 CW4010 Core Monitor Signals PLL Circuit System Configuration 6.1 CW4010 CCC Register 6.2 Lbus Controller Regist
Features
- MR4010 Functional Blocks 2.1 CW4010 Shell 2.2 Synchronous DRAM Controller (DRAMC) 2.3 SCbus to Local I/O Bus (Lbus) Controller (SCLC) 2.4 PLL Clock Circuit MR4010 Programming Model Signal.
MR4010 Datasheet
