LS7060C Datasheet | LSI

FEATURES : - DC to 50MHz Count Frequency - Byte Multiplexer - DC to 10MHz Byte Output Scan Frequency - +4.75V to +5.25V Operation (VDD - VSS) - Three-State Data Outputs; Bus, TTL and CMOS patible - Inputs TTL and CMOS patible - Unique Cascade Feature Allows Multiplexing of Successive Bytes of Data in Sequence in Multiple Counter Systems - Low Power Dissipation - LS7060C (DIP), LS7060C-S (SOIC) - See Figure 1 - LS7061C (DIP), LS7061C-S (SOIC) - See Figure 2 DESCRIPTION : The LS7060C/LS7061C are CMOS Silicon Gate, 32 bit Up Counters. The ICs include latches, multiplexer, byte output sequencer, eight three-state binary data output drivers and output cascading logic. .. DESCRIPTION OF OPERATION: 32 BIT BINARY UP COUNTER - LS7060C (LS7061C) The 32 bit static ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 20ns transition count of 32 ones to 32 zeros. Guaranteed count frequency is DC to 50MHz. See Figure 9A (9B) for Block Diagram. COUNT, ALT COUNT (LS7060C) Input count pulses to the 32 bit counter may be applied through either of these two inputs. The ALT COUNT input circuitry contains a Schmitt trigger network which allows proper counting with "infinitely" long clock edges. A high applied to either of these two inputs inhibits counting. COUNT (LS7061C) Input count pulses to the 32 bit counter may be applied through this input. This input is the most significant bit of the external data byte. RESET All 32 counter bits are reset to zero when RESET is brought low for a minimum of 20ns. RESET must be high for a minimum of 10ns before next valid count can be recorded. TEST COUNT Count pulses may be applied to the last 16 bits of the binary counter through this input, as long as Bit 16 of the counter is a low. The counter advances on the negative transition of these pulses. This input is intended to be used for test purposes. NOTE: LS7060C and LS7061C can directly replace LS7060 and LS7061 in all existing...