3256A Description
The ispLSI 3256A is a High-Density Programmable Logic Device containing 384 Registers, 128 Universal I/O pins, five Dedicated Clock Input Pins, eight Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows plete inter-connectivity between all of these elements.
3256A Key Features
- HIGH-DENSITY PROGRAMMABLE LOGIC
- 128 I/O Pins
- 11000 PLD Gates
- 384 Registers
- High Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc
- Small Logic Block Size for Random Logic
- HIGH-PERFORMANCE E CMOS TECHNOLOGY
- fmax = 90 MHz Maximum Operating Frequency
- tpd = 12 ns Propagation Delay