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3256E Datasheet PDF

Lattice Semiconductor 3256E

3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3256E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3256E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.
Part No. 3256E
Datasheet 3256E Download
Manufacturer
Lattice Semiconductor
Description In-System Programmable High Density PLD
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3256E datasheet page 1 preview

FEATURES

● HIGH-DENSITY PROGRAMMABLE LOGIC — 256 I/O Pins — 12000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
● HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100 MHz Maximum Operating Frequency — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
● IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable (ISP™) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging
● 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
● OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combin...
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