3256E Description
The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows plete inter-connectivity between all of these elements.
3256E Key Features
- HIGH-DENSITY PROGRAMMABLE LOGIC
- 256 I/O Pins
- 12000 PLD Gates
- 512 Registers
- High Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc
- Small Logic Block Size for Random Logic
- HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 100 MHz Maximum Operating Frequency
- tpd = 10 ns Propagation Delay