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3256E - In-System Programmable High Density PLD

General Description

The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements.

Key Features

  • HIGH-.

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Datasheet Details

Part number 3256E
Manufacturer Lattice Semiconductor
File Size 159.16 KB
Description In-System Programmable High Density PLD
Datasheet download datasheet 3256E Datasheet

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Other Datasheets by Lattice Semiconductor

Part Number Description
3256 High Density Programmable Logic
3256A In-System Programmable High Density PLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ispLSI 3256E ® In-System Programmable High Density PLD Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 256 I/O Pins — 12000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 100 MHz Maximum Operating Frequency — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable (ISP™) using Lattice ISP or Boundary Scan Test (IEEE 1149.