ISPLSI5256VA Overview
The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device.
ISPLSI5256VA Key Features
- SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC
- 3.3V Power Supply
- User Selectable 3.3V/2.5V I/O
- 12000 PLD Gates / 256 Macrocells
- Up to 192 I/O Pins
- 256 Registers
- High-Speed Global Interconnect
- SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance
- SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc
- PCB Efficient Ball Grid Array (BGA) Package Options