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ISPLSI5256VA - In-System Programmable 3.3V SuperWIDE High Density PLD

Description

The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.

Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs.

Features

  • SuperWIDE HIGH.

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Datasheet preview – ISPLSI5256VA

Datasheet Details

Part number ISPLSI5256VA
Manufacturer Lattice Semiconductor
File Size 311.45 KB
Description In-System Programmable 3.3V SuperWIDE High Density PLD
Datasheet download datasheet ISPLSI5256VA Datasheet
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Full PDF Text Transcription

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ispLSI 5256VA ® In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 192 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns, tsu3 (CLK2/3) = 3.5ns — TTL/3.3V/2.
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