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ispClock5406D Datasheet Zero Delay And Fan-out Buffer

Manufacturer: Lattice Semiconductor

Overview: ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2009 Preliminary Data Sheet.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • CleanClock™ PLL.
  • Ultra Low Period Jitter 2.5ps.
  • Ultra Low Phase Jitter 6.5ps.
  • Fully Integrated High-Performance PLL.
  • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback.
  • Up to 10 Programmable Fan-out Buffers.
  • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS.

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