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ispLSI2064E - In-System Programmable SuperFAST High Density PLD

Download the ispLSI2064E datasheet PDF. This datasheet also covers the ispLSI2064E-100LT100 variant, as both devices belong to the same in-system programmable superfast high density pld family and are provided as variant models within a single manufacturer datasheet.

General Description

The ispLSI 2064E is a High Density Programmable Logic Device.

The device contains 64 Registers, 64 Universal I/O pins, four Dedicated Input Pins, three Dedicated Clock Input Pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

Key Features

  • SuperFAST HIGH.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ispLSI2064E-100LT100_LatticeSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ispLSI2064E
Manufacturer Lattice Semiconductor
File Size 142.38 KB
Description In-System Programmable SuperFAST High Density PLD
Datasheet download datasheet ispLSI2064E Datasheet

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Other Datasheets by Lattice Semiconductor

Part Number Description
ISPLSI2064 In-System Programmable High Density PLD
ISPLSI2064A In-System Programmable High Density PLD
ISPLSI2064VE 3.3V In-System Programmable High Density SuperFAST PLD
ispLSI2064VL 2.5V In-System Programmable SuperFAST High Density PLD
ISPLSI2032 In-System Programmable High Density PLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ispLSI® 2064E In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functionally and JEDEC Upward Compatible with ispLSI 2064 Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.