LTC6950 Datasheet PDF | Linear Technology

Linear Technology LTC6950

The LTC6950 delivers the low phase noise clock signals demanded in high frequency, high resolution data acquisition systems. The frequency synthesizer contains afull low noise PLL core with a programmable reference divider (R), a programmable feedback divider (N), a phase/frequency detector (PFD) and a low noise charge pump (CP). The clock distribution section of the LTC6950 delivers up to five outputs based on the VCO input.

Part No.	LTC6950
Datasheet	LTC6950 Download
Manufacturer	Linear Technology
Description	1.4GHz Low Phase Noise / Low Jitter PLL
Buy	Stock & Price

FEATURES

LTC6950 1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution

DESCRIPTION

n Low Phase Noise and Jitter n Additive Jitter: 18fsRMS (12kHz to 20MHz) n Additive Jitter: 85fsRMS (10Hz to Nyquist) n EZSync™ Multichip Clock Edge Synchronization n Full PLL Core with Lock Indicator n –226dBc/Hz Normalized In-Band Phase Noise Floor n –274dBc/Hz Normalized 1/f Phase Noise n 1.4GHz Maximum VCO Input Frequency n Four Independent, Low Noise 1.4GHz LVPECL Outputs n One LVDS/CMOS Configurable Output n Five Independently Programmable Dividers Covering All Integers from 1 to 63 n Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63 n –40°C to 105°C Junction Temperature Range

APPLICATIONS

n Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems n Low Jitter Clock Generation and Distribution The LTC®6950 is a low phase noise integer-N frequency synthesizer core with clock distribution. Each output is individually programmed to divide the VCO input frequency by any integer from 1 to 63 and to delay the output by 0 to 63 VCO clock cycles.