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DSP32C - Digital Signal Processor

Description

Contents of the PDR register may fail to be transferred to memory during a DMA write operation when the falling edge of PEN or PWN aligns near the trailing edge of the output clock (CKO).

If an external device overwrites the PDR, the DMA transaction is not completed.

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Datasheet preview – DSP32C

Datasheet Details

Part number DSP32C
Manufacturer Lucent Technologies
File Size 0.98 MB
Description Digital Signal Processor
Datasheet download datasheet DSP32C Datasheet
Additional preview pages of the DSP32C datasheet.

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Full PDF Text Transcription

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Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issue 5 of the DSP32C. Issue 5 devices are identified by a device code of the form DSP32C-X35 (where X is replaced by R or F). The design consideration involves external writes to and reads from the parallel data register (PDR) with a system clock greater than 66 MHz. Problem Resolution PEN, PWN, and PGN may be synchronized with the DSP clock to eliminate this potential alignment problem. Figure 1 illustrates a circuit that may be used to synchronize these inputs. Figure 2 shows the associated timing. The synchronization circuit delays the rise and fall points of PEN, PWN, and PGN.
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