DSP32C Datasheet | Lucent Technologies

Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issue 5 of the DSP32C. Issue 5 devices are identified by a device code of the form DSP32C-X35 (where X is replaced by R or F). The design consideration involves external writes to and reads from the parallel data register (PDR) with a system clock greater than 66 MHz. Problem Resolution PEN, PWN, and PGN may be synchronized with the DSP clock to eliminate this potential alignment problem. Figure 1 illustrates a circuit that may be used to synchronize these inputs. Figure 2 shows the associated timing. The synchronization circuit delays the rise and fall points of PEN, PWN, and PGN. This added delay is equal to the maximum time of t CKOHCKOH + the cp to Q propagation delay of the F74 (t PLH or t PHL). For an 80 MHz CKI, the maximum delay would be 12.5 ns + the cp to Q delay of the F74. Subsequently, the user must ensure that other timing specifications listed in Table 1 and Table 2 are not violated. Problem Description Contents of the PDR register may fail to be transferred to memory during a DMA write operation when the falling edge of PEN or PWN aligns near the trailing edge of the output clock (CKO). If an external device overwrites the PDR, the DMA transaction is not pleted. The status of the parallel data full (PDF) flag and associated pin may be corrupted during this transaction. A DMA read transaction may fail if the falling edge of PEN or PGN aligns near the falling edge of CKO. The PDF flag and associated pin may not correctly assume a deasserted state. The failure occurs only when the DSP operates at a clock frequency greater than 66 MHz, and CKO is asynchronous with respect to the PEN, PWN, and PGN signals. To eliminate this potential problem, a synchronous clocking scheme is needed. This clocking scheme prevents PEN, PWN and PGN from falling a minimum of 3 ns before the falling edge of CKO. See Figure 2. DSP32C Digital Signal...