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Rev. 2.8
LY622568
256K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 2.0 Rev. 2.1
Rev. 2.2 Rev. 2.3 Rev. 2.4 Rev. 2.5 Rev. 2.6 Rev. 2.7
Rev. 2.8
Description Initial Issue Revised ISB1/IDR/Test Condition of ICC Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR Adding SL Spec.
Revised ABSOLUTE MAXIMUN RATINGS
Added ISB1/IDR values when TA = 25℃ and TA = 40℃ Revised ISB1 (MAX) of SL grade
Revised FEATURES & ORDERING INFORMATION Lead free
and green package available to Green package available
Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Revised -35ns to -45ns Spec.
Revised VDR
Revised PACKAGE OUTLINE DIMENSION in page 8/9/11 Revised ORDERING INFORMATION in page 12
Revised VIL(max) from 0.