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CHD408LVS - 4M-Bit Low Power Asynchronous SRAM

General Description

The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade’s patent pending SuperT-SRAM™ technology, fabricated with low-power 0.18µm process technology.

Key Features

  • Low power Low active and standby power for hand-held.

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Datasheet Details

Part number CHD408LVS
Manufacturer MIRA
File Size 137.37 KB
Description 4M-Bit Low Power Asynchronous SRAM
Datasheet download datasheet CHD408LVS Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CHD408LVS-55,70 CHD408LVW-55,70 Rev 2.2 Jul’03 4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™ LOW-POWER ASYNCHRONOUS SRAM DESCRIPTION The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade’s patent pending SuperT-SRAM™ technology, fabricated with low-power 0.18µm process technology. The CHD408LVS is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. CHD408LVS -55,70 is packaged in sTSOP-I packages, with normal and reverse lead-bending. sTSOP-I packages are available in dimensions of 8x12mm and 8x20mm. FEATURES • Low power Low active and standby power for hand-held applications. Single power supply.