CHD408LVW - 4M-Bit Low Power Asynchronous SRAM

This page provides the datasheet information for the CHD408LVW, a member of the CHD408LVS 4M-Bit Low Power Asynchronous SRAM family.

Datasheet Summary

Description

The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade’s patent pending SuperT-SRAM™ technology, fabricated with low-power 0.18µm process technology.

Features

Low power Low active and standby power for hand-held.

MIRA

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Datasheet Details

Part number	CHD408LVW
Manufacturer	MIRA
File Size	137.37 KB
Description	4M-Bit Low Power Asynchronous SRAM
Datasheet	CHD408LVW Datasheet
Additional preview pages of the CHD408LVW datasheet.

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Other Datasheets by MIRA

CHD408LVS - 4M-Bit Low Power Asynchronous SRAM

Full PDF Text Transcription

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CHD408LVS-55,70 CHD408LVW-55,70 Rev 2.2 Jul’03 4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™ LOW-POWER ASYNCHRONOUS SRAM DESCRIPTION The CHD408L is a family of low voltage, low power 4Mbit static RAMs organized as 512K-words by 8-bit, designed with Cascade’s patent pending SuperT-SRAM™ technology, fabricated with low-power 0.18µm process technology. The CHD408LVS is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. CHD408LVS -55,70 is packaged in sTSOP-I packages, with normal and reverse lead-bending. sTSOP-I packages are available in dimensions of 8x12mm and 8x20mm. FEATURES • Low power Low active and standby power for hand-held applications. Single power supply.

Published: Dec 15, 2005 |