MX25L12835F
Overview
- Supports Serial Peripheral Interface -- Mode 0 and Mode 3
- Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations
- 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four I/O mode) structure
- Protocol Support - Single I/O, Dual I/O and Quad I/O
- Latch-up protected to 100mA from -1V to Vcc +1V
- Fast read for SPI mode - Support clock frequency up to 133MHz for all protocols - Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions. - Configurable dummy cycle number for fast read operation
- Quad Peripheral Interface (QPI) available
- Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
- Programming : - 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
- Typical 100,000 erase/program cycles
