DS26502 Datasheet | Maxim Integrated

DESCRIPTION FEATURES The DS26502 is a building-integrated timing- G.703 2048k Hz Synchronization Interface supply (BITS) clock-recovery element. It also pliant functions as a basic T1/E1 transceiver. The - G.703 64k Hz Centralized (Option A) and receiver portion can recover a clock from T1, Codirectional Timing Interface pliant E1, 64k Hz posite clock (64KCC), and - G.703 Appendix II 64k Hz and 6312k Hz 6312k Hz synchronization timing interfaces. In Japanese Synchronization Interface T1 and E1 modes, the Synchronization Status pliant - Interfaces to Standard T1/J1 (1.544MHz) and Message (SSM) can also be recovered. The transmit portion can directly interface to T1, E1, E1 (2.048MHz) - Interface to CMI-Coded T1/J1 and E1 or 64KCC synchronization interfaces as well as - Short- and Long-Haul Line Interface source the SSM in T1 and E1 modes. The - Transmit and Receive T1 and E1 SSM DS26502 can translate between any of the Messages with Message Validation supported inbound synchronization clock rates to - T1/E1 Jitter Attenuator with Bypass Mode any supported outbound rate. A separate output - Fully Independent Transmit and Receive is provided to source a 6312k Hz clock. The Functionality device is controlled through a parallel, serial, or .. hardware controller port. - Internal Software-Selectable Receive- and Transmit-Side Termination for 75Ω/100Ω/110Ω/120Ω T1, E1, and posite Clock Interfaces APPLICATIONS - Monitor Mode for Bridging Applications BITS Timing - Accepts 16.384MHz, 8.192MHz, 4.096MHz, Rate Conversion or 2.048MHz Master Clock - 64k Hz, 8k HZ, and 400Hz Outputs in posite Clock Mode ORDERING INFORMATION - 8-Bit Parallel Control Port, Multiplexed or PART TEMP RANGE PIN-PACKAGE Nonmultiplexed, Intel or Motorola DS26502L 0°C to +70°C 64 LQFP - Serial (SPI) Control Port - Hardware Control Mode DS26502LN -40°C to +85°C 64 LQFP - Provides LOS, AIS, and LOF Indications Through Hardware Output Pins - Fast Transmitter-Output Disable Through Device Pin for Protection...