Overview: DS26504 T1/E1/J1/64KCC BITS Element
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Transmit and Receive T1 BOC SSM Messages with Receive Message Change of State and The DS26504 is a building-integrated timing-supply Validation Indication (BITS) clock-recovery element. It also functions as a § Transmit and Receive E1 Sa(n) Bit SSM basic T1/E1 transceiver. The receiver portion can Messages with Receive Message Change of State recover a clock from T1, E1, 64kHz posite clock Indication (64KCC), and 6312kHz synchronization timing § Crystal-Less Jitter Attenuator with Bypass Mode interfaces. In T1 and E1 modes, the Synchronization for T1 and E1 Operation Status Message (SSM) can also be recovered. The § Fully Independent Transmit and Receive transmit portion can directly interface to T1, E1, or Functionality 64KCC synchronization interfaces as well as source § Internal Software-Selectable Receive and the SSM in T1 and E1 modes. The DS26504 can Transmit Side Termination for translate between any of the supported inbound 75Ω/100Ω/110Ω/120Ω/133Ω synchronization clock rates to any supported § Monitor Mode for Bridging Applications outbound rate. The DS26504 can also accept an 8kHz § Accepts 16.384MHz, 12.8MHz, 8.192MHz, as well as a 19.44MHz reference clock. A separate 4.096MHz, 2.048MHz, or 1.544MHz Master output is provided to source a 6312kHz clock. The Clock device is controlled through a parallel, serial, or § 64kHz, 8kHz, and 400Hz Outputs in posite hardware controller port. Clock Mode ..
