MAX3629 Datasheet | Maxim Integrated

19-4467; Rev 0; 2/09 .. +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs General Description The MAX3629 is a low-jitter precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications. Maxim’s proprietary PLL design Features ultra-low jitter (0.4ps RMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment. The MAX3629 contains five LVDS outputs and three LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by pin control. - Crystal Oscillator Interface: 25MHz - OSC_IN Interface: PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz - Outputs: One LVDS Output at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELA) Four LVDS Outputs at 125MHz/156.25MHz/ 312.5MHz (Selectable with FSELB) Three LVCMOS Outputs at 125MHz/156.25MHz (Selectable with FSELB) - Low Phase Jitter: 0.4ps RMS (12k Hz to 20MHz) - Excellent PSNR - Operating Temperature Range: 0°C to +70°C Features Applications Ethernet Networking Equipment Typical Operating Circuit +3.3V ±5% Ordering Information PART TEMP RANGE 0°C to +70°C PIN-PACKAGE 32 TQFN-EP- MAX3629CTJ+ 10.5Ω 0.1μF 0.1μF 0.1μF 10μF VDDA 0.01μF VDDO_DIFF VDDO_SE Q0 Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω +Denotes a lead(Pb)-free/Ro HS-pliant package. - EP = Exposed pad. 100Ω...