MAX3679A Datasheet | Maxim Integrated

19-4858; Rev 0; 8/09 .. KIT ATION EVALU E L B AVAILA +3.3V, Low-Jitter Crystal to LVPECL Clock Generator General Description Features - Crystal Oscillator Interface: 25MHz - CMOS Input: 25MHz - Output Frequencies for Ethernet 62.5MHz, 125MHz, 156.25MHz, 312.5MHz - Low Jitter 0.14ps RMS (1.875MHz to 20MHz) 0.36ps RMS (12k Hz to 20MHz) - Excellent Power-Supply Noise Rejection - No External Loop Filter Capacitor Required The MAX3679A is a low-jitter precision clock generator with the integration of three LVPECL and one LVCMOS outputs optimized for Ethernet applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet applications. Maxim’s proprietary PLL design Features ultra-low jitter (0.36ps RMS) and excellent power-supply noise rejection, minimizing design risk for network equipment. Applications Ethernet Networking Equipment Ordering Information PART MAX3679AETJ+ TEMP RANGE -40°C to +85°C PIN-PACKAGE 32 TQFN-EP- Pin Configuration appears at end of data sheet. +Denotes a lead(Pb)-free/Ro HS-pliant package. - EP = Exposed pad. Typical Application Circuit +3.3V ±5% 10.5Ω 0.1μF 0.1μF 0.1μF 0.01μF 0.1μF 10μF 0.1μF MR VCC VCCA REF_IN IN_SEL QAC_OE QA_OE QB0_OE VCC QB1_OE BYPASS SELA1 SELA0 SELB1 SELB0 RES1 RES0 X_OUT VCCO_A VCCO_B VDDO_A QA_C 125MHz QA QA 125MHz 36Ω Z0 = 50Ω ASIC Z0 = 50Ω Z0 = 50Ω 50Ω...