MAX5866 Datasheet | Maxim Integrated

.. 19-3223; Rev 0; 2/04 KIT ATION EVALU E L B A AVAIL Ultra-Low-Power, High-Dynamic Performance, 60Msps Analog Front End General Description Features - Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs - Ultra-Low Power 80m W at f CLK = 60MHz (Rx Mode) 52.5m W at f CLK = 60MHz (Tx Mode) Low-Current Idle and Shutdown Modes - Excellent Dynamic Performance 48d B SINAD at f IN = 25MHz (ADC) 64.2d Bc SFDR at f OUT = 6MHz (DAC) - Excellent Gain/Phase Match ±0.2° Phase, ±0.05d B Gain at f IN = 25MHz (ADC) - Internal/External Reference Option - +2.7V to +3.3V Digital Output Level (TTL/CMOS patible) - Multiplexed Parallel Digital Input/Output for ADCs/DACs - Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm) - Evaluation Kit Available (Order MAX5865EVKIT) The MAX5866 ultra-low-power, highly integrated analog front end is ideal for portable munication equipment such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5866 integrates dual, 8-bit receive ADCs and dual, 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs’ analog I-Q input amplifiers are fully differential and accept 1V P-P full-scale signals. Typical I-Q channel phase matching is ±0.2° and amplitude matching is ±0.05d B. The ADCs feature 48d B SINAD and 70.1d Bc spurious-free dynamic range (SFDR) at f IN = 25MHz and f CLK = 60MHz. The DACs’ analog I-Q outputs are fully differential with ±400m V full-scale output, and 1.4V mon-mode level. Typical I-Q channel phase matching is ±0.4° and gain matching is ±0.1d B. The DACs also feature dual, 10-bit resolution with 64.2d Bc SFDR, at f OUT = 6MHz and f CLK = 60MHz. The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface controls power-down and transceiver modes of operation. The typical operating power is 96m W at f CLK = 60MHz with the ADCs and DACs operating simultaneously in transceiver mode. The...