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MAX3396E - Dual-/Quad-/Octal-Level Translators

Download the MAX3396E datasheet PDF. This datasheet also covers the MAX3394E variant, as both devices belong to the same dual-/quad-/octal-level translators family and are provided as variant models within a single manufacturer datasheet.

General Description

The MAX3394E/MAX3395E/MAX3396E bidirectional level translators provide level shifting required for data transfer in a multivoltage system.

Key Features

  • 10mA current-sink and 15mA currentsource drivers to isolate capacitive loads from lower current drivers. In open-drain systems, slew-rate enhancement enables fast data rates with larger pullup resistors and increased bus load capacitance. Externally applied voltages, VCC and VL, set the logic-high levels for the device. A logic-low signal on one I/O side of the device appears as a logic-low signal on the opposite I/O side, and vice-versa. Each I/O line is pulled up to VCC or VL by an internal pu.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MAX3394E-MaximIntegrated.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MAX3394E/MAX3395E/ MAX3396E ±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry General Description The MAX3394E/MAX3395E/MAX3396E bidirectional level translators provide level shifting required for data transfer in a multivoltage system. Internal slew-rate enhancement circuitry features 10mA current-sink and 15mA currentsource drivers to isolate capacitive loads from lower current drivers. In open-drain systems, slew-rate enhancement enables fast data rates with larger pullup resistors and increased bus load capacitance. Externally applied voltages, VCC and VL, set the logic-high levels for the device. A logic-low signal on one I/O side of the device appears as a logic-low signal on the opposite I/O side, and vice-versa.