MAX19711 Datasheet | Maxim Integrated

19-0527; Rev 0; 5/06 KIT ATION EVALU E L B AVAILA 10-Bit, 11Msps, Full-Duplex Analog Front-End General Description Features - Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit, 11Msps Tx DAC - Ultra-Low Power 37.5m W/42.7m W at f CLK = 4.915MHz/11MHz, FD Mode 24.3m W at f CLK = 11MHz, Slow Rx Mode 34.5m W at f CLK = 11MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes - Integrated CDMA Filters with > 64d Bc Stopband Rejection - Programmable Tx DAC mon-Mode DC Level and I/Q Offset Trim - Excellent Dynamic Performance SNR = 54.8d B at f IN = 1.875MHz (Rx ADC) SFDR = 75d Bc at f OUT = 620k Hz (Tx DAC) - Three 12-Bit, 1µs Aux-DACs - 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging - Excellent Gain/Phase Match ±0.01° Phase, ±0.01d B Gain (Rx ADC) at f IN = 1.87MHz - Multiplexed Parallel Digital I/O - Serial-Interface Control - Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable - Miniature 56-Pin Thin QFN Package (7mm x 7mm x 0.8mm) The MAX19711 is an ultra-low-power, highly integrated mixed-signal analog front-end (AFE) ideal for CDMA munication applications operating in full-duplex (FD) mode. Optimized for high dynamic performance and ultra-low power, the device integrates a dual 10-bit, 11Msps receive (Rx) ADC; dual 10-bit, 11Msps transmit (Tx) DAC with CDMA baseband filters; three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control; and a 10-bit, 333ksps housekeeping aux-ADC. The typical operating power in FD mode is 37.5m W/42.7m W at a 4.915MHz/11MHz clock frequency. The Rx ADCs feature 54.8d B SNR and 74.2d Bc SFDR at 1.875MHz input frequency with an 11MHz clock frequency. The analog I/Q input amplifiers are fully differential and accept 1.024V P-P full-scale signals. Typical I/Q channel matching is ±0.01° phase and ±0.01d B gain. The Tx DACs with CDMA lowpass filters feature -3d B cutoff frequency of 1.3MHz and > 64d Bc stopband rejection at f IMAGE = 4.285MHz at f CLK = 4.915MHz. The analog I-Q full-scale output...