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MAX19711 - Analog Front-End

Key Features

  • Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit, 11Msps Tx DAC.
  • Ultra-Low Power 37.5mW/42.7mW at fCLK = 4.915MHz/11MHz, FD Mode 24.3mW at fCLK = 11MHz, Slow Rx Mode 34.5mW at fCLK = 11MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes.
  • Integrated CDMA Filters with > 64dBc Stopband Rejection.
  • Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim.
  • Excellent Dynamic Performance SNR = 54.8dB at fIN = 1.875MHz (Rx ADC) SFDR = 75dBc at fOUT = 620kH.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-0527; Rev 0; 5/06 KIT ATION EVALU E L B AVAILA 10-Bit, 11Msps, Full-Duplex Analog Front-End General Description Features ♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit, 11Msps Tx DAC ♦ Ultra-Low Power 37.5mW/42.7mW at fCLK = 4.915MHz/11MHz, FD Mode 24.3mW at fCLK = 11MHz, Slow Rx Mode 34.5mW at fCLK = 11MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes ♦ Integrated CDMA Filters with > 64dBc Stopband Rejection ♦ Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim ♦ Excellent Dynamic Performance SNR = 54.8dB at fIN = 1.875MHz (Rx ADC) SFDR = 75dBc at fOUT = 620kHz (Tx DAC) ♦ Three 12-Bit, 1µs Aux-DACs ♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging ♦ Excellent Gain/Phase Match ±0.01° Phase, ±0.01dB Gain (Rx ADC) at fIN = 1.