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MAX9125 - Quad LVDS Line Receivers

Key Features

  • o Integrated Termination Eliminates Four External Resistors (MAX9126) o Pin Compatible with DS90LV032A o Guaranteed 500Mbps Data Rate o 300ps Pulse Skew (max) o Conform to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Low 70µA Shutdown Supply Current o Fail-Safe Circuit MAX9125/MAX9126 The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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19-1908; Rev 0; 5/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Receivers with Integrated Termination General Description Features o Integrated Termination Eliminates Four External Resistors (MAX9126) o Pin Compatible with DS90LV032A o Guaranteed 500Mbps Data Rate o 300ps Pulse Skew (max) o Conform to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Low 70µA Shutdown Supply Current o Fail-Safe Circuit MAX9125/MAX9126 The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100Ω.