MG82F6D32 Datasheet | Megawin

8051-Based MCU MG82F6D64/32 Data Sheet Version: 1.01 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice.  Megawin Technology Co., Ltd. 2020 All rights reserved. 2020/09 version 1.01 MG82F6D64/32 Version: 1.01 megawin Features MG82F6D64/32 - 1-T 80C51 Central Processing Unit - MG82F6D64/32 with 64K/32K Bytes flash ROM ━ ISP memory zone could be optioned as 0.5KB/1.0KB~7.5KB ━ Flexible IAP size by software configured ━ Code protection for flash memory access ━ Flash write/erase cycle: 20,000 ━ Flash data retention: 100 years at 25°C ━ Default MG82F6D64 Flash space mapping  AP Flash default mapping (61.5KB, 0000h~F5FFh)  IAP Flash default mapping (1.0KB, F600h~F9FFh)  ISP Flash default mapping (1.5KB, FA00h~FFFFh), ISP Boot code ━ Default MG82F6D32 Flash space mapping  AP Flash default mapping (29.5KB, 0000h~75FFh)  IAP Flash default mapping (1.0KB, 7600h~79FFh)  ISP Flash default mapping (1.5KB, 7A00h~7FFFh), ISP Boot code - Data RAM: ━ On-chip 256 bytes scratch-pad RAM ━ MG82F6D64 - 3840 bytes expanded RAM (XRAM) ━ MG82F6D32 - 1792 bytes expanded RAM (XRAM) ━ Support page select on XRAM access - Dual data pointer - External Memory Bus interface (EMB) ━ Only support No Address mode access (LCD 8080 I/F) - Provide one channel DMA engine ━ P2P, M2P, P2M ━ Memory target: on-chip XRAM & EMB ━ Peripheral target: UART0/1/2/3, SPI, TWI0/I2C0, I2C1, ADC12, EMB & CRC16 ━ Timer 5 and Timer 6 are used for DMA, but it also can be traded as independent timer when DMA not in use - Interrupt controller ━ 24 sources, four-level-priority interrupt capability ━ Four external interrupt inputs, n INT0, n INT1, n INT2 and n INT3 with glitch filter ━ All external interrupts support High/Low level or Rising/Falling edge trigger - Total 14/ 17(with split mode) timers in MG82F6D64, and total 13/15(with split mode) timers in MG82F6D32 ━ RTC Timer and WDT Timer ━ Timer...