MPC82L52
Overview
- 1-T 80C51 Central Processing Unit
- MPC82E/L52 with 8K Bytes flash ROM ━ ISP memory zone could be optioned as 1.0KB, 2.0KB or 3.0KB ━ Two level code protections for flash memory access ━ Flash write/erase cycle: 20,000 ━ Flash data retention: 100 years at 25℃ ━ MPC82E/L52 Flash space mapping (Default); AP Flash（0000h~17FFh）; IAP Flash（1800h~1BFFh）; ISP Flash（1C00h~1FFFh）（ISP Boot code）
- On-chip 256 bytes scratch-pad RAM
- Interrupt controller ━ 7 sources, four-level-priority interrupt capability ━ Two external interrupt inputs, INT0 and INT1
- Two 16-bit timer/counters, Timer 0 and Timer 1. ━ X12 mo
