SY100E196 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT Precision Edge® Precision SESYd Y1g1000e EE®119966 SY10E196 Features s Up to 2ns delay range s Extended 100E VEE range of - 4.2V to - 5.5V s ≈20ps digital step resolution s Linear input for tighter resolution s >1GHz bandwidth s On-chip cascade circuitry s 75KkΩ input pulldown resistor s Fully patible with Motorola MC10E/100E196 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E196 are programmable delay chips (PDCs) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjustment organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. The FTUNE input takes an analog coltage and applies it to an internal linear ramp for reducing the 20s resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. PIN NAMES Pin IN/IN EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE FTUNE VCCO Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Minimum Delay Set Maximum Delay Set Cascade Signal Linear Voltage Input VCC to Output M9999-032006 hbwhelp@micrel. or (408) 955-1690 Rev.:...