SY100H602 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS 9-BIT LATCHED TTL-TO-ECL SY10H602 SY1S0YH10600H2602 Features s 9-bit ideal for byte-parity applications s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s Dual supply s 3.5ns max. D to Q s PNP TTL inputs for low loading s Choice of ECL patibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully patible with MC10H/100H602 s Available in 28-pin PLCC package DESCRIPTION The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H602 Features D-type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post-latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level. The 10H version is patible with MECL 10KH ECL logic levels. The 100H version is patible with 100K levels. BLOCK DIAGRAM ENECL D0 D1 D2 D3 TTL D4 D5 D6 D7 D8 LEN MR DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ...