Datasheet4U Logo Datasheet4U.com

SY10EL32V - 5V/3.3V / 2 DIVIDER

Download the SY10EL32V datasheet PDF. This datasheet also covers the SY100EL32V variant, as both devices belong to the same 5v/3.3v / 2 divider family and are provided as variant models within a single manufacturer datasheet.

General Description

The SY10/100EL32V are integrated ÷ 2 dividers.

The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device.

If used, the VBB output should be bypassed to ground with a 0.01µF capacitor.

Key Features

  • s s s s s s 3.3V and 5V power supply options 510ps propagation delay 3.0GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SY100EL32V_MicrelSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SY10EL32V
Manufacturer Micrel Semiconductor
File Size 49.07 KB
Description 5V/3.3V / 2 DIVIDER
Datasheet download datasheet SY10EL32V Datasheet

Full PDF Text Transcription for SY10EL32V (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SY10EL32V. For precise diagrams, and layout, please refer to the original PDF.

5V/3.3V ÷ 2 DIVIDER ClockWorks™ SY10EL32V SY100EL32V FEATURES s s s s s s 3.3V and 5V power supply options 510ps propagation delay 3.0GHz toggle frequency High bandwidth ...

View more extracted text
ptions 510ps propagation delay 3.0GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package DESCRIPTION The SY10/100EL32V are integrated ÷ 2 dividers. The differential clock inputs and the VBB allow a differential, single-ended or AC-coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01µF capacitor. Also note that the VBB is designed to be used as an input bias on the EL32V only; the VBB output has limited current sink and source capability. The reset pin is asynchronous and is asserted on the rising edge.