SY10ELT22 Overview
The SY10/100ELT22 are dual TTL-to-differential PECL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the tranlation of a clock and a data signal.
SY10ELT22 Key Features
- 300ps typical propagation delay <100ps output-to-output skew Differential PECL outputs PNP TTL inputs for minimal loadin