SY10ELT23 Datasheet | Micrel Semiconductor

Micrel NOT REMENDED FOR NEW DESIGNS DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR Precision Edge® Precision SEY1d0g Ee LT®23 SY1S0YE1L00TE2L3T23 SY100ELT23 Features s 3.0ns typical propagation delay s <500ps typical output-to-output skew s Differential PECL inputs s 24m A TTL outputs s Flow-through pinouts s Internal input 50kΩ pulldown resistors s Available in 8-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM D0 1 D0 2 PECL D1 3 D1 4 8 VCC 7 Q0 TTL 6 Q1 5 GND SOIC TOP VIEW Precision Edge® DESCRIPTION The SY10/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew dual gate design of the ELT23 makes it ideal for applications which require the translation of a clock and a data signal. The ELT23 is available in both ECL standards: the 10ELT is patible with positive ECL 10H logic levels, while the 100ELT is patible with positive ECL 100K logic levels. PIN NAMES Pin Qn Dn VCC GND Function TTL Outputs Differential PECL Inputs +5.0V Supply Ground Precision Edge is a registered trademark of Micrel, Inc. Rev.: J Amendment: 0 Issue Date: February...