SY10ELT23 Datasheet | Synergy

.. SEMICONDUCTOR SYNERGY DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR Clock Works™ SY10ELT23 Clock Works™ SY100ELT23 SY10ELT23 SY100ELT23 Features s s s s s s s 3.0ns typical propagation delay <500ps typical output-to-output skew Differential PECL outputs 24m A TTL outputs Flow-through pinouts ESD protection of 2000V Available in 8-pin SOIC package DESCRIPTION The SY10/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT23 makes it ideal for applications which require the tranlation of a clock and a data signal. The ELT23 is available in both ECL standards: the 10ELT is patible with positive ECL 10H logic levels, while the 100ELT is patible with positive ECL 100K logic levels. PIN CONFIGURATION/BLOCK DIAGRAM PIN NAMES Pin Function TTL Outputs Differential PECL Inputs +5.0V Supply Ground D0 D0 D1 D1 1 2 PECL 3 4 TTL 8 7 6 5 VCC Q0 Q1 GND Qn Dn VCC GND SOIC TOP VIEW © 1998 Synergy Semiconductor Corporation Rev.: F Amendment: /0 5-232 Issue Date: August, 1998 SEMICONDUCTOR SYNERGY Clock Works™ SY10ELT23...