SY10H351 Datasheet | Micrel Semiconductor

Micrel, Inc. QUAD TTL/NMOS-to-PECL TRANSLATOR Features s Single 5V power supply s All VCC pins isolated on chip s Differentially drive balanced lines s t PD 1.3ns typical s Fully patible with MC10H351 s Available in 20-pin PLCC package BLOCK DIAGRAM D1 7 D0 8 D3 12 D2 14 MON 9 STROBE 1 /Q1 2 Q1 5 /Q0 4 Q0 16 /Q3 17 Q3 19 /Q2 18 Q2 VCC (+5 VDC) = Pins 6, 11, 15, 20; GND = Pin 10 DESCRIPTION The SY10H351 is a quad translator for interfacing data between a saturated logic selection and the PECL section of digital systems when only a +5.0V VDC power supply is available. The SY10H351 has TTL/NMOS patible inputs and PECL plementary open-emitter outputs that allow use as an inverting/non-inverting translator or as a differential line driver. When the mon strobe input is at a low logic level, it forces all true outputs to the PECL low logic state (≈ +3.2V) and all inverting outputs to the PECL high logic state (≈ 4.1V). The SY10H351 can also be used with the SY10H350 to transmit and receive TTL/NMOS information differentially via balanced twisted pair lines. PIN NAMES Pin D0 - D3 Q0 - Q3 /Q0 - /Q3 VCC1 VCCE VCCT VCC2 mon Strobe GND Function Inputs Outputs Inverted outputs PECL VCC (5.0V) PECL VCC (5.0V) TTL VCC (5.0V) PECL VCC (5.0V) mon Strobe Ground M9999-032906 hbwhelp@micrel. or (408) 955-1690 Rev.: B Amendment: /0 Issue Date: March 2006 Micrel, Inc. PACKAGE/ORDERING INFORMATION Q2 Q3 /Q3 VCC2 D2 Ordering Information(1) /Q2 19 VCCE 20 /Q1 1 Q1 2 NC 3 18 17 16 15 14 Top View PLCC J20-1 456 7...