SY10H601 Datasheet | Micrel Semiconductor

Micrel, Inc. NOT REMENDED FOR NEW DESIGNS 9-BIT ECL-TO-TTL WITH 3-STATE ENABLE SY1S0YH10600H1601 SY100H601 Features s 9-bit ideal for byte-parity applications s 3-state TTL outputs s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s ECL and TTL 3-state control inputs s 4.8ns max. delay into 50p F, 9.6ns into 200p F (all outputs switching) s PNP TTL inputs for low loading s Choice of ECL patibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully patible with MC10H/100H601 s Available in 28-pin PLCC package DESCRIPTION The SY10/100H601 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 48m A TTL output stage and AC performance is specified into both a 50p F and 200p F load capacitance. For the 3-state output disable, both ECL and TTL control inputs are provided, allowing maximum design flexibility. The 10H version is patible with MECL 10KH ECL logic levels. The 100H version is patible with 100K levels. BLOCK DIAGRAM OEECL OETTL D0 D1 D2 D3 D4 D5 D6 D7 D8 Q0 Q1 Q2 Q3 Q4 TTL Q5 Q6 Q7 Q8 PIN NAMES Pin GND VCCE VCCT VEE D0- D8 Q0- Q8 OEECL OETTL Function TTL Ground (0V) ECL VCC (0V) TTL Supply (+5.0V) ECL Supply (- 5.2/- 4.5V) Data Inputs (ECL) Data Outputs (TTL) 3-State Control (ECL) 3-State Control (TTL) M9999-032906 hbwhelp@micrel. or (408) 955-1690 Rev.: E Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10H601 SY100H601 PACKAGE/ORDERING...