SY10H603 Datasheet | Micrel Semiconductor

Micrel, Inc. 9-BIT LATCHED ECL-TO-TTL SY1S0YH10600H3603 SY100H603 Features s 9-bit ideal for byte-parity applications s 3-state TTL outputs s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s Dual supply s 6.0ns max. delay into 50p F, 12ns into 200p F (all outputs switching) s PNP TTL inputs for low loading s Choice of ECL patibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully patible with MC10H/100H603 s Available in 28-pin PLCC package DESCRIPTION The SY10/100H603 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 48m A TTL output stage and AC performance is specified into both a 50p F and 200p F load capacitance. Latching is controlled by Latch Enable (LEN) and Master Reset (MR) resets the latches. A HIGH on OEECL sends the outputs into the high impedance state. All control inputs are ECL level. The 10H version is patible with MECL 10KH ECL logic levels. The 100H version is patible with 100K levels. BLOCK DIAGRAM OEECL D0 D1 D2 D3 D4 D5 D6 D7 D8 LEN MR DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN M9999-032906 hbwhelp@micrel. or (408)...