Micrel SY100E151
The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK1 or CLK2 (or both) go HIGH.
| Part No. |
SY100E151 |
| Datasheet |
SY100E151
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| Manufacturer |
 Micrel |
| Description |
6-BIT D REGISTER |
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FEATURES
s 1100MHz toggle frequency s Extended 100E VEE range of –4.2V to –5.46V s Differential outputs s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E151 s Available in 28-pin PLCC package DESCRIPTION
Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 CLK1 CLK2 M R D R D R D R D R D R D R Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 PIN NAMES Pin D0–D5 CLK1, CLK2 MR Q0–Q5 Q0–Q5 VCCO Function Data Inputs Clock Inputs Master Reset True Outputs Inverting Outputs VCC to Output M9999-052108 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: H Amendment: /0 Issue Date: May 2008 Micrel, Inc. SY10E151 SY100E151 PACKAGE/ORDERING INFORMATION Ordering Information(1) MR CLK2 CLK1 NC VCCO Q5 Q5 D5 D4 D3 VEE D2...
