Microchip Technology DSPIC33FJ06GS101
16-bit Digital Signal Controllers
| Part No. | DSPIC33FJ06GS101 |
|---|---|
| Datasheet | DSPIC33FJ06GS101 Download |
| Manufacturer |  Microchip Technology |
| Description | 16-bit Digital Signal Controllers |
| Buy | Stock & Price |
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16-Bit Digital Signal Controllers (up to 16-Kbyte Flash and up to 2-Kbyte SRAM) with High-Speed PWM, ADC and Comparators Operating Conditions
● 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
● 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
● 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS Core: 16-Bit dsPIC33F CPU
● Code-Efficient (C and Assembly) Architecture
● Two 40-Bit Wide Accumulators
● Single-Cycle (MAC/MPY) with Dual Data Fetch
● Single-Cycle Mixed-Sign MUL plus Hardware Divide
● 32-Bit Multiply Support Clock Management
● ±2.0% Internal Oscillator
● Programmable PLLs and Oscillator Clock Sources
● Fail-Safe Clock Monitor (FSCM)
● Independent Watchdog Timer (WDT)
● Fast Wake-up and Start-up Power Management
● Low-Power Management modes (Sleep, Idle, Doze)
● Integrated Power-on Reset and Brown-out Reset High-Speed PWM
● Up to Four PWM Pairs with Independent Timing
● Dead Time for Rising and Falling Ed
● 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
● 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
● 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS Core: 16-Bit dsPIC33F CPU
● Code-Efficient (C and Assembly) Architecture
● Two 40-Bit Wide Accumulators
● Single-Cycle (MAC/MPY) with Dual Data Fetch
● Single-Cycle Mixed-Sign MUL plus Hardware Divide
● 32-Bit Multiply Support Clock Management
● ±2.0% Internal Oscillator
● Programmable PLLs and Oscillator Clock Sources
● Fail-Safe Clock Monitor (FSCM)
● Independent Watchdog Timer (WDT)
● Fast Wake-up and Start-up Power Management
● Low-Power Management modes (Sleep, Idle, Doze)
● Integrated Power-on Reset and Brown-out Reset High-Speed PWM
● Up to Four PWM Pairs with Independent Timing
● Dead Time for Rising and Falling Ed
