PIC32CMLS00 Datasheet | Microchip Technology

features - 32 KB Boot ROM System - Power-on Reset (POR) and programmable Brown-out Detection (BOD) - 16-channel Direct Memory Access Controller (DMAC) - 12-channel event system for Inter-peripheral Core-independent Operation - CRC-32 generator Low-Power and Power Management - Active, Idle, Standby with partial or full SRAM retention and off sleep modes: - Active mode (< 40 μA/MHz for PL0, < 60 μA/MHz for PL2) - Idle mode (< 15 μA/MHz) with 1.5 μs wake-up time - Standby with Full SRAM retention (1.7 μA) with 2.7 μs wake-up time - Off mode (< 100 n A) - Static and dynamic power gating architecture - Sleepwalking peripherals - Two performance levels - Embedded Buck/LDO regulator with on-the-fly selection Security and Safety - Up to eight input pins and eight output pins for anti-tampering detections - Data Flash - Optimized for secure storage - Address and Data Scrambling with user-defined key (optional) - Tamper erase of scrambling key and of one user-defined row - Silent access for data read noise reduction Security and Safety (Continued) - Trust RAM - Address and Data scrambling with user-defined key - Anti-tamper Active Shield on physical Trust RAM - Tamper Erase of scrambling key and Trust RAM data - Silent access for data read noise reduction - Data remanence prevention - Peripherals - One True Random Number Generator (TRNG) - AES-256/192/128, SHA-256, and GCM cryptography accelerators (optional) - Secure pin multiplexing capability to isolate secure munication channels with external devices from the non-secure application (optional) - Trust Zone for flexible hardware isolation of memories and peripherals (optional) - Up to five regions for the Flash - Up to two regions for the Data Flash - Up to two regions for the SRAM - Individual security attribution for each peripheral, I/O, external interrupt line, and Event System...