PIC32CMLS60 Overview
2.64 CoreMark/MHz and 1.03 DMIPS/MHz Single-cycle hardware multiplier Hardware divider Nested Vector Interrupt Controller (NVIC) Memory Protection Unit (MPU) Stack Limit Checking TrustZone® for ARMv8-M (optional) Memories 512/256 KB Flash 16/8 KB Data Flash Write-While-Read (WWR) section for non-volatile data storage 64/32 KB SRAM 512 bytes TrustRAM with physical protection.
PIC32CMLS60 Key Features
- 32 KB Boot ROM
- Power-on Reset (POR) and programmable Brown-out Detection (BOD)
- 16-channel Direct Memory Access Controller (DMAC)
- 12-channel event system for Inter-peripheral Core-independent Operation
- CRC-32 generator
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes
- Active mode (< 40 μA/MHz for PL0, < 60 μA/MHz for PL2)
- Idle mode (< 15 μA/MHz) with 1.5 μs wake-up time
- Standby with Full SRAM retention (1.7 μA) with 2.7 μs wake-up time
- Off mode (< 100 nA)