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SY100EP195V - 3.3V/5V 1.6 GHz Programmable Delay

General Description

The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q.

This delay can vary from about 2.1 ns to about 10.8 ns.

The input can be PECL, LVPECL, NECL, or LVNECL.

Key Features

  • Pin-for-Pin, Plug-In Compatible to the ON Semiconductor MC100EP195.
  • Maximum Frequency >1.6 GHz.
  • Programmable Range: 2.1 ns to 10.8 ns.
  • 10 ps Increments.
  • PECL Mode Operating Range: VCC = 3.0V to 5.5V with VEE = 0V.
  • NECL Mode Operating Range: VCC = 0V with VEE =.
  • 3.0V to.
  • 5.5V.
  • Open Input Default State.
  • Safety Clamp on Inputs.
  • A Logic-High on the /EN pin will Force Q to Logic-Low.
  • D[0:10] Can.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SY100EP195V 3.3V/5V 1.6 GHz Programmable Delay Features • Pin-for-Pin, Plug-In Compatible to the ON Semiconductor MC100EP195 • Maximum Frequency >1.6 GHz • Programmable Range: 2.1 ns to 10.8 ns • 10 ps Increments • PECL Mode Operating Range: VCC = 3.0V to 5.5V with VEE = 0V • NECL Mode Operating Range: VCC = 0V with VEE = –3.0V to –5.5V • Open Input Default State • Safety Clamp on Inputs • A Logic-High on the /EN pin will Force Q to Logic-Low • D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs • VBB Output Reference Voltage • Available in a 32-Pin TQFP Package Applications • Clock De-skewing • Timing Adjustment • Aperture Centering General Description The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q.