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TP2104 - P-Channel Vertical DMOS FET

General Description

The TP2104 low-threshold, Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process.

Key Features

  • High Input Impedance and High Gain.
  • Low-Power Drive Requirement.
  • Ease of Paralleling.
  • Low CISS and Fast Switching Speeds.
  • Excellent Thermal Stability.
  • Integral Source-Drain Diode.
  • Free from Secondary Breakdown.

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Full PDF Text Transcription (Reference)

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TP2104 P-Channel Enhancement-Mode Vertical DMOS FET Features • High Input Impedance and High Gain • Low-Power Drive Requirement • Ease of Paralleling • Low CISS and Fast Switching Speeds • Excellent Thermal Stability • Integral Source-Drain Diode • Free from Secondary Breakdown Applications • Logic-Level Interfaces (Ideal for TTL and CMOS) • Solid-State Relays • Analog Switches • Power Management • Telecommunication Switches General Description The TP2104 low-threshold, Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices.