Description
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
Features
- VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V.
- Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data www. DataSheet4U. com capture (x16 has two.
- one per byte).
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
- Differential clock inputs (CK and CK#).
- Commands entered on each positive CK edge.
- DQS edge-aligned with data for READs; centeraligned with data for WRIT.
46V32M16 Datasheet
