MT53E1536M32D4 Datasheet | Micron Technology

Features LPDDR4X/LPDDR4 SDRAM MT53E768M64D4, MT53E1536M64D8, MT53E768M32D2, MT53E1536M32D4 Features This data sheet is for LPDDR4X and LPDDR4 unified product based on LPDDR4X information. As for LPDDR4 setting, refer to General LPDDR4 Specification at the end of this data sheet. - Ultra-low-voltage core and I/O power supplies - VDD1 = 1.70- 1.95V; 1.80V nominal - VDD2 = 1.06- 1.17V; 1.10V nominal - VDDQ = 0.57- 0.65V; 0.60V nominal or VDDQ = 1.06- 1.17V; 1.10V nominal - Frequency range - 2133- 10 MHz (data rate range per pin: 4266- 20 Mb/s) - 16n prefetch DDR architecture - 8 internal banks per channel for concurrent operation - Single-data-rate CMD/ADR entry - Bidirectional/differential data strobe per byte lane - Programmable READ and WRITE latencies (RL/WL) - Programmable and on-the-fly burst lengths (BL = 16, 32) - Directed per-bank refresh for concurrent bank opera- tion and ease of mand scheduling - Up to 8.5 GB/s per die x16 channel - On-chip temperature sensor to control self refresh rate - Partial-array self refresh (PASR) - Selectable output drive strength (DS) - Clock-stop capability - Ro HS-pliant, “green” packaging - Programmable VSS (ODT) termination - Single-ended CK and DQS support Options Marking - VDD1/VDD2/VDDQ: 1.80V/1.10V/0.60V or 1.10V - Array configuration - 768 Meg x 32 (2 channels x 16 I/O) - 1536 Meg x 32 (2 channels x 16 I/O) - 768 Meg x 64 (4 channels x 16 I/O) - 1536 Meg x 64 (4 channels x 16 I/O) - Device configuration - 768M16 x 2 die in package - 768M16 x 4 die in package - 768M16 x 8 die in package - FBGA “green”...