ZL30151 Datasheet | Microsemi

Features - Input Clocks - Three inputs, two differential/CMOS, one CMOS - Any input frequency from 1k Hz to 650MHz (1k Hz to 300MHz for CMOS) - Inputs continually monitored for activity and frequency accuracy - Automatic or manual reference switching - Low-Bandwidth DPLL - Programmable bandwidth, 1Hz to 500Hz - Attenuates jitter up to several UI - Freerun or holdover on loss of all inputs - Hitless reference switching - High-resolution holdover averaging - Digitally controlled phase adjustment - Low-Jitter Fractional-N APLL and 3 Outputs - Any output frequency from <1Hz to 650MHz - High-resolution fractional frequency conversion with 0ppm error - Easy-to-configure, encapsulated design requires no external VCXO or loop filter ponents - Each output has independent dividers - Output jitter is typically 0.16 to 0.28ps RMS (12k Hz-20MHz integration band) - Outputs are CML or 2x CMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL 3-Input, 3-Output Any-to-Any Line Card PLL with Ultra-Low Jitter Data Sheet January 2018 Ordering Information ZL30151LDG1 ZL30151LDF1 32 Pin QFN Trays 32 Pin QFN Tape and Reel Matte Tin Package size: 5 x 5 mm -40C to +85C - In 2x CMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz) - Per-output supply pin with CMOS output voltages from 1.5V to 3.3V - Precise output alignment circuitry and peroutput phase adjustment - Per-output enable/disable and glitchless start/stop (stop high or low) - General Features - Automatic self-configuration at power-up from internal EEPROM; up to four configurations pin-selectable - Numerically controlled oscillator mode - Zero-delay mode with external feedback - SPI or I2C processor Interface - Easy-to-use evaluation software Applications...