ZL30244 Description
Register Map: Section.
ZL30244 Key Features
- Two Independent APLL Channels
- Four Input Clocks Per Channel
- One crystal/CMOS input
- Two differential/CMOS inputs
- One single-ended/CMOS input
- Any input frequency from 9.72MHz to 1250MHz
- Clock selection by pin or register control
- Low-Jitter Fractional-N APLL and 3 Outputs Per Channel
- Any output frequency from <1Hz to 1035MHz
- High-resolution fractional frequency conversion
ZL30244 Applications
- Frequency conversion and frequency synthesis in a wide variety of equipment types