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ZL40234 - Low Additive Jitter 4 Output LVPECL/LVDS/HCSL Fanout Buffer

General Description

6 Functional Description 8 Clock Inputs 8 Clock Outputs 11 Crystal Oscillator Input 12 Termination of unused inputs and outputs 12 Power Consumption 12 Power Supply Filtering 13 Power Supplies and Power-up Sequence 13 Device Control 14 Typical device performance 15 AC and DC Electrical Char

Key Features

  • 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal.
  • Four differential LVPECL/LVDS/HCSL outputs.
  • One LVCMOS output.
  • Ultra-low additive jitter: 24fs (in 12kHz to 20MHz integration band at 625MHz clock frequency).
  • Supports clock frequencies from 0 to 1.6GHz.
  • Supports 2.5V or 3.3V power supplies for LVPECL, LV.

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Data Sheet ZL40234 Low Skew, Low Additive Jitter, 4 Output LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output Features • 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal • Four differential LVPECL/LVDS/HCSL outputs • One LVCMOS output • Ultra-low additive jitter: 24fs (in 12kHz to 20MHz integration band at 625MHz clock frequency) • Supports clock frequencies from 0 to 1.6GHz • Supports 2.5V or 3.3V power supplies for LVPECL, LVDS or HCSL outputs • Supports 1.5V, 1.8V, 2.5V or 3.