Datasheet Summary
Data Sheet
Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL Fanout Buffer with one LVCMOS output
Features
- 3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal
- Five differential LVPECL/LVDS/HCSL outputs and one LVCMOS output
- Ultra-low additive jitter: 24fs (integration band 12kHz to 20MHz at 625MHz clock frequency)
- Supports clock frequencies from 0 to 1.6GHz
- Supports 2.5V or 3.3V power supplies for LVPECL, LVDS or HCSL outputs
- Supports 1.5V, 1,8V, 2.5V or 3.3V power supplies for LVCMOS output
- Embedded Low Drop Out (LDO) Voltage...