AS5SP128K36 Datasheet | Micross

Plastic Encapsulated Microcircuit 4.5Mb, 128K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect Features - Synchronous Operation in relation to the input Clock - 2 Stage Registers resulting in Pipeline operation - On chip address counter (base +3) for Burst operations - Self-Timed Write Cycles - On-Chip Address and Control Registers - Byte Write support - Global Write support - On-Chip low power mode [powerdown] via ZZ pin - Interleaved or Linear Burst support via Mode pin - Three Chip Enables for ease of depth expansion without Data Contention. - Two Cycle load, Single Cycle Deselect - Asynchronous Output Enable (OE) - Three Pin Burst Control (ADSP, ADSC, ADV) - 3.3V Core Power Supply - 3.3V/2.5V IO Power Supply - JEDEC Standard 100 pin TQFP Package - Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges - Ro Hs pliant options available DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd...