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MT5C1001 - 1M x 1 SRAM

General Description

The MT5C1001 employs low power, high-performance silicon-gate CMOS technology.

Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability.

Key Features

  • High Speed: 20, 25, 35, and 45.
  • Battery Backup: 2V data retention.
  • Low power standby.
  • Single +5V (+10%) Power Supply.
  • Easy memory expansion with CE and OE options.
  • All inputs and outputs are TTL compatible.
  • Three-state output.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SRAM MT5C1001 Limited Availability 1M x 1 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-92316 • MIL-STD-883 FEATURES • High Speed: 20, 25, 35, and 45 • Battery Backup: 2V data retention • Low power standby • Single +5V (+10%) Power Supply • Easy memory expansion with CE and OE options. • All inputs and outputs are TTL compatible • Three-state output OPTIONS • Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access MARKING -20 -25 -35 -45 -55* -70* • Package(s) Ceramic DIP (400 mil) Ceramic LCC Ceramic Flatpack Ceramic SOJ C No. 109 EC No. 207 F No. 303 DCJ No.