MT8941 Datasheet | Mitel Networks Corporation

® CMOS ST-BUS™ FAMILY MT8941 Advanced T1/CEPT Digital Trunk PLL Features - - Provides T1 clock at 1.544 MHz locked to an 8 k Hz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and STBUS clock and timing signals locked to an internal or external 8 k Hz reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 d B,100 Hz=43 d B, 5 to 40 k Hz ≥ 64 d B Jitter-free “FREE-RUN” mode Unmitted two-input NAND gate Low power CMOS technology ISSUE 5 July 1993 Ordering Information MT8941AE MT8941AP 24 Pin Plastic DIP 28 Pin PLCC -40° C to +85°C - - - - - Description The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 k Hz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 k Hz frame pulse signal. The MT8941 offers improved jitter performance over the MT8940. The two devices also have some functional differences, which are listed in the section on “Differences between MT8941 and MT8940”. Applications - - Synchronization and timing control for T1 and CEPT digital trunk transmission links ST- BUS clock and frame pulse source F0i DPLL #1 C12i 2:1 MUX CVb Variable Clock Control CV ENCV MS0 MS1 MS2 MS3 C8Kb Mode Selection Logic Frame Pulse Control Input Selector 4.096 MHz Clock Control DPLL #2 Clock Generator Ai Bi 2.048 MHz Clock Control F0b C4b C4o ENC4o C16i C2o C2o ENC2o Yo Figure 1 - Functional Block Diagram 3-43 CMOS 24 PIN PDIP Figure 2 - Pin Connections Pin Description Pin #...