Datasheet Details
| Part number | MT8941 |
|---|---|
| Manufacturer | Mitel Networks Corporation |
| File Size | 246.58 KB |
| Description | CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL |
| Datasheet |
 MT8941 Datasheet
|
|
|
General Description
The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz.
Key Features
- Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and STBUS clock and timing signals locked to an internal or external 8 kHz reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz ≥ 64 dB Jitter-free “FREE-RUN” mode Uncommitted two-input NAND gate Low power CMOS technology ISSUE 5 July 1993 Ordering Information MT894.